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Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances
Klaes, D.; Moers, J.; Tönnesmann, A. et al.
1998In Proceedings of the 28th European Solid State Devices Research Conference, Bordeaux, France
 

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Disciplines :
Electrical & electronics engineering
Identifiers :
UNILU:UL-CONFERENCE-2009-421
Author, co-author :
Klaes, D.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Moers, J.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Tönnesmann, A.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Grimm, M.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Wickenhäuser, S.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Vescan, L.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Marso, Michel ;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Kordoš, P.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
Lüth, H.;  Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany
External co-authors :
yes
Language :
English
Title :
Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances
Publication date :
1998
Event name :
28th European Solid State Devices Research Conference, Bordeaux, France
Event date :
1998
Main work title :
Proceedings of the 28th European Solid State Devices Research Conference, Bordeaux, France
Pages :
568-571
Available on ORBilu :
since 30 March 2015

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